1. Technical Field
The present invention relates generally to a method for planarization during integrated circuit fabrication. More particularly, the present invention relates to an improved method of determining planarization endpoint during chemical-mechanical polishing.
2. Background Art
Planarization is a critical step in integrated circuit fabrication. Planarity is often necessary for the next level processing. For example, photolithography is more difficult without a planar surface, and a planar surface yields better metal coverage in the sputtering technique. One way to planarize is known as chemical-mechanical polishing (CMP). In CMP, a polishing pad and slurry are used to grind down a surface on a wafer. A CMP slurry consists of small particles of controlled size, usually silicon dioxide, in a disbursing solution. The liquid acts as both a lubricant and a travel medium for the particles.
Regardless of the planarization method utilized, a common requirement is knowing when to stop planarization. This could be accomplished by measuring the material thickness before planarization and periodically checking thickness during planarization until the desired thickness, known as planarization endpoint, is achieved. This is not always practical and may slow production. In addition, when the planarization method is CMP, the wafer would have to be cleaned of slurry before each such measurement. This extra step makes inspection of large numbers of wafers in production utilizing CMP expensive.
FIG. 1 depicts a cross-sectional view of an integrated circuit 10 including a substrate 12 covered with insulation layer 14. Metal pattern 16 on insulation layer 14 is conformally covered with a second insulation layer 18.
If planarization of insulation layer 18 is to be done, knowing when to stop planarizing is essential. If planarization ends too soon, the surface will not be completely planar, as shown in FIG. 1 at dashed line 20. At the other extreme, if planarization goes beyond end point 24, metal will be exposed and may be thinned, as shown at dashed line 22.
FIG. 2 depicts the integrated circuit 10 of FIG. 1 before and after a prior art planarization method known as reactive ion etching is performed. A layer of photoresist 26 is added on top of insulation layer 18. As seen in FIG. 2, photoresist layer 26 is not planar. In the prior art method, etching removes resist 26 and insulation 18 down to level 28. As is known in the art, level 28 takes substantially the same shape as resist layer 26 had. Thus, while almost planarized, the prior art method does not give optimum planarization due to the flow characteristics of the photoresist.
Therefore, a need exists for a CMP process which allows rapid inspection of wafers to see if planarization endpoint has been achieved, and is easily incorporated into the fabrication process.